There is known a method employed in a semiconductor device such as a DRAM (Dynamic Random Access Memory), in which a memory chip having memory cell arrays and a logic chip having a logic circuit including sense amplifiers and word drivers are fabricated on two different wafers, respectively, and the resultant two wafers are hybrid bonded. According to this method, the memory cell array and logic circuit can be fabricated by separate processes, thereby allowing the individual process conditions to be optimized.
However, the arrangement pitch of bit lines or sub-word lines formed on a memory chip is significantly smaller than the arrangement pitch of bonding electrodes used in the hybrid bonding. Therefore, in semiconductor devices of this type, both the memory chip and the logic chip require a wiring layer for pitch conversion. Details of this are disclosed in US 2015/0287706 A1 filed by the present inventor. The memory chip disclosed in US 2015/0287706 A1 has a configuration in which a plurality of memory cell arrays are laid out in a matrix (in both the bit line direction and the sub-word line direction), so that a wiring for transmitting a signal asynchronous with operation of the memory cell array passes a sense amplifier region or a sub-word driver region, with the result that noise may easily be superimposed on the sub-word line or bit line.